Assistant Professor Dr. Vassos Soteriou, CUT’s post-doctoral fellow Dr. Arseniy Vitkovskiy, and colleagues from the Texas A&M University in the USA have published their study titled “Use it or lose it: wear-out and lifetime in future chip multiprocessors” in the premier IEEE/ACM 2013 International Symposium on Microarchitecture (Micro). Micro has a typical acceptance rate of 15%-18% and is among the most influential conferences in computer architecture.
In this paper, the research team developed critical Network-on-Chip (NoC) router path models for Hot Carrier Injection and Negative Bias Temperature Instability-induced transistor physical wear due to stresses caused by realistic multi-threaded workloads, and applied them onto the Chip Multi-Processor (CMP) interconnect microarchitecture. A key finding from this modeling being that, counter to prevailing wisdom, wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. The research team then developed a novel wearout-decelerating scheme in which NoC routers under low load have their wearout-sensitive components exercised, with experimental evaluation results subsequently showing that the proposed design yields a 13.8X-65X increase in CMP lifetime.
IEEE/ACM International Symposium on Microarchitecture (Micro) publication
Assistant Professor Dr. Vassos Soteriou, CUT’s post-doctoral fellow Dr. Arseniy Vitkovskiy, and colleagues from the Texas A&M University in the USA have published their study titled “Use it or lose it: wear-out and lifetime in future chip multiprocessors” in the premier IEEE/ACM 2013 International Symposium on Microarchitecture (Micro). Micro has a typical acceptance rate of 15%-18% and is among the most influential conferences in computer architecture.
In this paper, the research team developed critical Network-on-Chip (NoC) router path models for Hot Carrier Injection and Negative Bias Temperature Instability-induced transistor physical wear due to stresses caused by realistic multi-threaded workloads, and applied them onto the Chip Multi-Processor (CMP) interconnect microarchitecture. A key finding from this modeling being that, counter to prevailing wisdom, wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. The research team then developed a novel wearout-decelerating scheme in which NoC routers under low load have their wearout-sensitive components exercised, with experimental evaluation results subsequently showing that the proposed design yields a 13.8X-65X increase in CMP lifetime.
